Responsibilities

• Micro-architect and design modules and subsystems,
• Design using formal tools i.e., model checking using formal tools
• Implement design by performing synthesis, timing closure, lint, CDC, UPF
• Participate in FPGA emulation, FPGA and silicon bring up

Qualifications

• Experience with RTL development, Synthesis, Timing analysis, power analysis
• Exposure to FPGA emulation platforms, silicon bring up, board debug
• Proficient with EDA tools, Python and Tcl
• Knowledge of formal methods
• BTech/MTech in EE/CS with any level of experience