Sr Engineer, ASIC Physical Design

Hyderabad, India


  • Physical Design of complex datapath and control blocks
  • Develop new techniques and flows to rapidly prototype hardware blocks
  • Develop flows that allow for detailed power estimation
  • Work with design team to understand placement and recommend implementation options
  • Interact and engage with external teams to drive as well as deliver subsystems leading to chip tapeout


  • BTech/MTech EE/CS with 8+ Years of Physical Design experience.
  • Extensive knowledge of
    • Automated synthesis, Technology mapping, Place-and-Route and Layout techniques
    • Physical verification and quality checks like LVS, DRC, IR drop
    • Clock tree synthesis, Power mesh design, Signal integrity
    • Latest foundry nodes up to 7nm
  • Hands on experience with
    • Synthesis, Automatics Place-and-route, Full Chip STA, IO Planning, Full Chip Floorplan, Power Mesh creation, Bump Planning, RDL Routing, Low power design flows
  • Strong understanding of advanced digital design architectures and clocking structures to help manage timing and physical design constraints
  • Ability to work with designers to analyze and explore physical implementation options for complex designs.
  • Basic knowledge of DFT techniques and implications on Physical design
  • Desired tool familiarity
    • Industry standard PnR, Synthesis etc tools, TCL Scripting
  • Strong communication skills and good team player

Please send a resume and cover letter

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