Engineer, ASIC Verification

Hyderabad, India


  • Develop verification environments for modules, subsystems, top level and FPGA
  • Build models, checkers and random test frameworks using SystemVerilog and UVM
  • Participate in Low power analysis (UPF), power estimation, C modeling
  • Perform lint, CDC, code coverage, functional coverage
  • Formal verification of modules using SVA assertions


  • Experience in verifying complex subsystems and ASICs
  • Experience with building scalable verification environments from scratch
  • Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.
  • Exposure to FPGA emulation platforms, silicon bringup, board debug
  • BTech/MTech in EE/CS with any level of experience

Please send a resume and cover letter

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