Responsibilities

• Develop verification environments for modules, subsystems, top level and FPGA
• Build models, checkers and random test frameworks using SystemVerilog and UVM
• Participate in Low power analysis (UPF), power estimation, C modeling
• Perform lint, CDC, code coverage, functional coverage
• Formal verification of modules using SVA assertions

Qualifications

• Experience in verifying complex subsystems and ASICs
• Experience with building scalable verification environments from scratch
• Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.
• Exposure to FPGA emulation platforms, silicon bringup, board debug
• BTech/MTech in EE/CS with any level of experience